VHDL Workshop

Our Intention

is to support our customer in:
understanding the VHDL Language
familiarisation with the possibilities
understanding Design Strategy (training based on examples)
familiarisation with Synthesis and Simulation with VHDL

Agenda

Introduction
QuartusII
Objects
Signals and Variables
RTL/Technology Map Viewer
Libraries
Examples
Hierarchy
Testbenching
Modelsim
Optimization
Pragma, Attribute and Assignments
Coding Style Guide
Debug Tools
Literature